OPINION: It’s early morning, you’re preparing for the day ahead and thinking about life’s important conundrums.
Is there enough muesli left for the week? Do you have enough time to catch the bus? Are you going to meet that looming deadline at work? How are we going to continue improving electronic technology beyond today’s generation?
OK, well maybe not that last one, but if you stop for a second and think about our daily conveniences you might just realise that problems such as this are already part of our lives.
Let’s consider smartphones. At the end of the 1990s computers using Pentium II processors took up your desk and ran at about 50% the computational speed of that phone.
In the early 1970s they filled a room, cost a fortune and ran at roughly 0.02% the brain power of your Angry-Bird-launching, GPS-mapping, Facetime-ing companion.
The developments that have made all of this possible have followed Moore’s Law, which simply means we’ve been able to double the amount of electronics on the same size of chip space once every year and a half or so.
This has been done by continually shrinking transistors, and creating faster and more affordable technology.
So how much further can we go?
As it turns out, we are already approaching the fundamental limits of scaling, and the (quantum) effects of electrons themselves are becoming more important in the design of tomorrow’s devices.
As semiconductor device dimensions shrink, so must the metal interconnects between the devices. It is within this new regime of metal wires only a few hundreds of atoms across that the effects of dissimilar metal junctions may prove to be much more important than they previously were.
Today we are not far from this point, with the International Technology Roadmap for Semiconductors predicting the interconnecting line widths on semiconductor chips will be less than 16 nanometres (1nm = 10-9 m) within the next decade.
To put that size into perspective, 16nm is about 6.5 times the diameter of DNA or 1/10,000 the diameter of the average human hair.
In a recent paper, scientists studied how readily electrons flow from one type of metal to another at very small scales.
What the researchers found is surprising. As they made the metal junction small enough the electrical flow from tungsten to gold (a common junction in CMOS technology – a type of integrated circuit) did not decrease linearly, but instead dropped off dramatically.
This means the interconnect materials used in the coming generations of small-scale electronics will need to be carefully chosen to better match their electronic structures.
The research team – a collaboration of physicists from McGill University in Canada and researchers at General Motors R&D in the US – began by using a technique known as Field Ion Microscopy (FIM) to create an accurate image of the nanometer-scale tungsten tip they would use to contact a gold surface.
Knowing the profile of the tip, they then pressed or “nanoindented” the tip into a gold surface. By characterising the hardness of the surface, they could also determine the contact area.
The process forms electrical junctions of less than 500 atoms, through which current is then passed.
The resulting current was found to be much less than anticipated for the area that it was passing through.
To gain insight into the underlying cause of this decrease, the team then turned to molecular dynamics simulations. Using these simulations they created an atomic model of the tip to compare to the experimental FIM image and investigate the generation of atomic stacking faults (an imperfection in the arrangement of atoms) in the gold surface caused by the tip’s contact.
With knowledge of the tip’s profile in hand, the team turned to state-of-the-art quantum transport characteristics to study how electrons travel through the gold-tungsten interface at the atomic level.
The junction’s conductance density – a measure of electrical conductivity per unit area – was found to be four times lower than the conductance density of either gold or tungsten on their own.
This surprising decrease is explained by the orbital mismatch between tungsten (where free electrons orbit in a d-orbital) and gold (an s-orbital metal) in systems at sufficiently small-length scales. (Simply put, orbitals refer to the predicted location of an atom’s electrons in orbit around the nucleus).
Orbital mismatch of metals has thus far not been a problem in the larger junctions of conventional CMOS technology.
As mentioned, the team’s finding indicates careful consideration of interconnect materials will be necessary as semiconductor devices are shrunk further.
As we approach ballistic scales – where the dimensions of the metal wires become comparable to the wavelength of electrons – device resistance to electrical flow will be dominated by junctions of metals with dissimilar electronic structures.
So tomorrow morning when you’re considering life’s little conundrums, think for a moment about the electronics you take for granted and the researchers who are working tirelessly in this area.
Dr Adam Burke is a Senior Research Associate in the Nanoelectronics Group, UNSW.